The present invention relates to a method for contacting a chip with a conductor arrangement and also to a conductor arrangement, in particular a transponder antenna, an intermediate carrier or the like, with a carrier substrate for accommodating the chip and with a chip having chip terminal faces formed thereon, wherein a conductor material layer is formed on the carrier substrate, wherein the conductor material layer forms a conductor arrangement having at least two conductors which are connected to each other in a chip contact area, wherein an insulating gap is formed in the chip contact area such that mutually electrically insulated conductor terminal faces of the conductor are formed, and wherein the chip terminal faces are contacted with the conductor terminal faces.
Such methods for contacting a chip are regularly employed in the field of RFID technology, for instance in the production of transponder labels. A carrier substrate for the production of the transponder labels is made of a plastic material in the type of a thin film and serves in particular for accommodating a transponder antenna. The transponder antenna can basically be formed on the carrier substrate using the etching, imprinting or wire embedding technology. In the case of an antenna produced with the aid of an etching process, a chip having chip terminal faces formed thereon is directly placed on conductor terminal faces of the antenna and is connected, respectively contacted, with the same in an electrically conducting manner. Alternatively, the chip can be contacted with an intermediate carrier which is equally composed of a carrier substrate having conductor terminal faces and which has comparatively large antenna conductor terminal faces which in turn can be contacted with antenna conductors being produced for instance using the wire embedding technology. Thus, the intermediate carrier having the chip corresponds to a chip module which can be placed and contacted particularly easily due to the large antenna conductor terminal faces.
A problem encountered in the direct contacting of the chip with conductor terminal faces is to ensure accurate positioning of the chip. The conductor terminal faces are separated from each other by means of an insulating gap produced by an etching process, wherein during the positioning the chip straddles the insulating gap and with its corresponding chip terminal faces completely abuts against the conductor terminal faces. Depending on the material of the conductor material layer, the width of the insulating gap cannot be infinitely miniaturized using the known etching methods, in particular due to the aspect that the etching process results in an indefinite, respectively irregular, contour of the conductor terminal faces. Thus the chip needs to be positioned relatively accurately with its chip terminal faces on the conductor terminal faces, if the chip terminal faces are to be prevented from resting against the irregular peripheral region of the conductor terminal faces. In fact, it would also be possible to produce conductor terminal faces with a relatively regular contour if for instance copper were used for producing the conductor material layer. However, copper is relatively expensive compared to other materials and thus is unsuitable for mass production of conductor arrangements, as is required for instance in the case of labels.
The chips currently used for RFID labels regularly feature an edge length of approx. 600 μm, so that sufficiently accurate positioning of the chip on the conductor terminal faces being spaced apart by the insulating gap is still possible within acceptable tolerances. Hence, for instance a relative position of the chip transverse to the insulating gap can vary by approx. 80 μm. As a result of the technical progress, it will soon be possible to produce chips with an edge length of up to 300 μm. Even in the case where the width of the insulating gap and of the chip terminal faces is reduced, said chips require a much more accurate positioning with a positioning tolerance of for instance approx. 15 μm. Said small positioning tolerance is determined by the width of the insulating gap, which cannot be arbitrarily miniaturized in the known etching process.